1. Field of the Invention
The invention relates in general to systems for generating integrated circuit (IC) layouts and in particular to a system for generating a layout for an IC having two or more identical modules.
2. Description of Related Art
An IC fabricator typically provides an IC designer with a cell library describing a set of standard components (cells) such as transistors, gates, input/output ports and other devices that an IC designer can incorporate into an IC design. The IC designer then produces an IC design in the form of a netlist referencing instances of library cells to be included in the IC and referencing the conductive paths (nets) that are to interconnect terminals of the cell instances. The netlist can be hierarchical in nature with cell instances combining to form modules and with lower level modules and cell instances combining to form higher-level modules. After producing the netlist, the designer employs a placement and routing (P&R) tool to generate a layout for the IC indicating where each cell instance is to be placed within the IC and indicating how the nets interconnecting the cell instances are to be routed. The P&R tool also obtains the internal layout of each cell from the cell library and incorporates it into the IC layout.
The placement and routing process can be time-consuming for large ICs because a P&R tool will often have to iteratively generate many layout alternatives before finding one satisfying all spatial, timing and other constraints on the IC design. Since the time required to generate a layout tends to increase geometrically with the number of cell instances included the IC, designers often find that it can be helpful to divide a netlist design into several partitions and to separately lay out each partition. Such partitioning can speed up the placement and routing process because a P&R tool can often more quickly lay out N partitions of a design having an average of M cell instances each than to lay out an entire N×M cell IC at once.
A netlist may describe an IC as including several logically identical modules, each formed by similar sets of cell instances interconnected in a similar manner. For example, a netlist might describe an IC having a set of identical arithmetic logic units (ALUs) forming a data processing array. Since identical modules could have identical layouts, it is possible to reduce the time a P&R tool requires to generate an IC layout by having it generate a layout for only one of the modules (the “master” module) and then copying the layout for that module to produce a layout for each similar (“clone”) module.
FIG. 1 depicts a typical IC layout process flow for an IC having several identical modules. At step 10, an IC designer uses floor-planning tools to create a floor plan for the IC identifying the shape and positions of various areas of the layout. A typical floor plan can identify any of the following four types of areas within an IC layout:                A “hard block” area is an area of the layout to receive a circuit, such as for example a memory, for which a layout already exists. A P&R tool copies the pre-existing layout of the circuit into the hard block area and does not place any other cell instances in that area.        A “hard fence” area is an area of the layout exclusively reserved for cell instances forming one or more particular modules of the IC design. A P&R tool must place all cell instances belonging to modules assigned to a hard fence area in that hard fence area and must not place cell instances belonging to other modules of the IC in that hard fence area.        A “region” is an area of a layout in which one or more modules assigned to the region are to be placed. A P&R tool must place all cell instances of modules assigned to a region within that region, but may also place cell instances of other modules in that region.        A “guide block” is an area of a layout that acts as a guide for placing a module assigned to the guide block in the P&R tool is biased towards placing cell instances of that module within or near the guide block. However, the P&R tool is not required to place all cell instances of the module within the guide block, and may place cell instances of other modules in the guide block.        
Floor planning tools can automatically generate floor plans having guide blocks for selected modules, and the floor plan provided at step 10 includes a separate guide block for the master and each clone.
At step 12, the design engineer alters the floor plan to redefine the guide blocks for the master and the clones as hard fence areas so that the P&R tool will place the master and each clone by itself in an identifiable area of the layout. The design engineer will also redefine as hard fence areas guide blocks for any other modules that are to be separate partitions of the design. A P&R tool then generates a trial placement plan for the entire IC in accordance with the floor plan (step 14). Note that since the P&R tool independently lays out the master and each clone within their respective hard fence areas, they will not all have the same placement. Thereafter the P&R tool generates a trial routing plan describing the approximate routes of the nets interconnecting cell instances (step 16). The design engineer then uses various tools to verify that the logic implemented by the layout matches the logic described by the netlist and to verify that the layout meets various timing and spatial constraints (step 18). If the layout fails to meet its constraints, the process returns to one of steps 10, 14 or 16 to modify the floor plan, the trial placement or the trial routing. The process continues to iterate through steps 10–18 until it arrives at a trial layout passing all verification tests.
At this point (step 20), the designer partitions the netlist into several smaller netlists, including a set of base level partitions and a top-level partition. Each base level partition corresponds to a separate hard fence area of the floor plan and describes the module(s) assigned to that hard fence area. The top-level partition includes all portions of the design not included in any base level partition. The master and each of the clones and various other modules are also treated as separate partitions. As part of the partitioning process, the design engineer develops a pin assignment plan for each partition indicating points at which nets are to cross boundaries of each partition based on the trial routing plan provided at step 16. Since the IC specification typically places timing constraints on various signal paths within the IC that may extend through more than one partition, the design engineer also develops a timing budget at step 22 allocating separate portions of the timing constraint on each signal path to each of the various partitions through which the signal path may extend.
The design engineer then (step 22) employs a P&R tool to separately lay out the master partition and any other partition other than the clone partitions. After generating the clone layouts by copying the master layout (step 23), the P&R tool generates a layout for the top level partition based on a modified original floor plan (step 24) wherein the base level partitions are designated as hard blocks having the detailed layouts established at steps 22 and 23.
After generating the detailed top-level layout, the design engineer may use various tools to verify that the detailed layout meets all constraints (step 26). If the detailed layout fails to meet its constraints, the process will revert to any of steps 20, 22 or 24 to modify the pin assignment plan or timing budget, to modify the layout of one or more of the partitions, or to modify the top level layout in an attempt to meet all verification tests. In some cases, it may be necessary to revert all the way back to step 10 to modify the original floor plan. The layout process ends following step 26 when the detailed layout passes all verification tests. Note that copying the master module layout into the clone module layouts at step 23 helps to shorten the time needed to generate the detailed layout.
We can think of the trial layout generated at steps 12–16 as a prediction of what the detailed layout generated at steps 20–24 will look like. If the trial layout is a good predictor of the detailed layout, then trial layout verification carried out at step 18 will be a good predictor of the outcome of the detailed layout verification carried out at step 26. Since iterations through the detailed layout process (steps 22–26) consume more time than iterations through the trail layout process (steps 12–16), we want to the extent possible to use iterations though the trial layout process rather than iterations through the detailed layout process to resolve layout problems. Thus, it is important for the trial layout to be a good predictor of what the detailed layout will look like, without being too time-consuming to produce.
One difficulty with the prior art layout process of FIG. 1 is that in the trial layout, the master and clone modules are independently placed and routed at steps 14 and 16, and the time required to generate independent layouts for the clones unnecessarily adds to the time required to generate the trial layout. Note also that in the trial layout the clone layouts do not match the master module layout, whereas in the detailed layout the clone layouts are copies of the master layout. Thus, the trial layout is not always a good predictor of the detailed layout with respect to the clone modules.